RTL / FPGA Engineer
5–7 years · Full-time
The RTL / FPGA Engineer role at QiCAP is a hardware design position for engineers who push trading logic down into silicon, where latency is measured in nanoseconds rather than microseconds. You will design and verify FPGA logic in Verilog and SystemVerilog, take it through synthesis, timing closure, and place and route, and prove it with UVM-based verification. The designs sit directly on high-speed network paths, so comfort with 10G, 25G, and 100G Ethernet, PCIe, and AXI is central to the work, as is the resource and clock-domain discipline that real hardware imposes. We expect roughly five to seven years of RTL experience and a background in electrical, electronics, or computer engineering. Prior exposure to trading or low-latency networking hardware is a strong advantage, and scripting in Python, TCL, or Bash to automate the build and verification flow is part of the job.
What you’ll own
- Design FPGA logic in Verilog and SystemVerilog for nanosecond-scale trading paths
- Own synthesis, timing closure, place and route, and resource optimisation
- Build and run UVM-based verification for the blocks you design
- Implement and debug high-speed protocol interfaces — 10G/25G/100G Ethernet, PCIe, and AXI
- Automate build and verification flows with Python, TCL, or Bash
What we look for
- Roughly five to seven years of RTL design experience
- A degree in Electrical, Electronics/ECE, or Computer Engineering
- Strong Verilog and SystemVerilog; VHDL useful
- UVM verification experience
- Working knowledge of Xilinx Vivado, Intel Quartus, Vitis, and simulators such as VCS, ModelSim, QuestaSim, or Verilator
- Experience with trading or low-latency networking hardware is a strong advantage